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Recently, "On-chip Distributed Architectures" (ODCA) appeared as a solution for capitalizing on the high-integration capabilities of modern on-chip technologies. As distinct instances of such architectures we discuss networks-on-chip (NOC) and segmented buses (SB). The latter is the focus of this presentation.
We start by introducing the basic architectural characteristics of the ODCA followed by describing the current state-of-the art. While more traditional approaches are still applicable to solve point problems, an overall methodology for ODCA does not exist. Component design for ODCA has reached maturity, and, as a result, many implementation aspects are now well understood. However, the problem resides now in obtaining efficient application mapping on an ODCA platform. Directions to be followed in this scope can be identified as:
We introduce our own perspective towards a "generic" (SB illustrated) ODCA methodology. Starting at high levels of abstraction, where modeling principles are discussed, we analyze different phases of the proposed design flow, considering the results of solutions offered by the mathematical analysis, expressing requirements for libraries, etc.