Most telecommunication systems employed to day utilize modulation techniques that require the transceiver to be capable of accurately estimating the phase of the transmission signal. The frequency synthesizer is a key element and extensively utilized to synthesize frequencies for such radio-frequency communication systems. A common topology for the frequency synthesizer is the charge-pump based phase-locked loop. The development and design of frequency synthesizer is known to be a complex and time-consuming task, aggravated by the vast difference in frequencies between the output and the internal signals. It is often necessary to perform long transient simulations with short time steps to achieve reliable results. In most modern frequency synthesizers the phase detection circuits are capable of detecting both the frequency and phase difference. Such phase detectors are collectively known as phase-frequency detectors and generally employ some kind of memory functionality. The inherited memory in the phase-frequency detectors rouse the need for new models describing the synthesizer. This project treat the many design difficulties that concerns the frequency synthesizer, such as settling time, power consumption, amplitude variations, tuning range and phase noise properties.