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Power- and Performance-Aware IP Mapping for NoC-Based MPSoC Platforms

Fulltext:


Authors:

Khalid Latif , Amir-Mohammad Rahmani , Tiberiu Seceleanu, Hannu Tenhunen

Research group:

Industrial Software Engineering

Publication Type:

Conference/Workshop Paper

Venue:

The 17th IEEE International Conference on Electronics, Circuits, and Systems. Athens, Greece, December 12-15, 2010

Publisher:

IEEE

Abstract

In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media applications are time critical, where traffic must be delivered on time in order to operate properly. Proper task allocation or placement of IP cores at layout time is very important to meet such application requirements. Apart from meeting the application requirements, it also lowers the traffic congestion, power consumption and Average Packet Latency (APL). For task allocation or IP placement, the prioritization criteria has been proposed, which is used in next step to map the application on MPSoC platform. The proposed technique shows significant improvement in system performance and reduction in power consumption. To estimate the efficiency, the video conference encoding application and MPEG4 video encoder were mapped to 5x5 and 4x4 NoC mesh. Up to 11% reduction in power consumption and 20% reduction in APL has been observed as compared to other proposed mapping techniques.

Bibtex

@inproceedings{Latif2032,
author = {Khalid Latif and Amir-Mohammad Rahmani and Tiberiu Seceleanu and Hannu Tenhunen},
title = {Power- and Performance-Aware IP Mapping for NoC-Based MPSoC Platforms},
editor = {IEEE},
pages = {760--763},
month = {December},
year = {2010},
booktitle = {The 17th IEEE International Conference on Electronics, Circuits, and Systems. Athens, Greece, December 12-15, 2010},
publisher = {IEEE},
url = {http://www.es.mdu.se/publications/2032-}
}