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Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers.

Fulltext:


Authors:

Khalid Latif , Tiberiu Seceleanu, Hannu Tenhunen

Research group:

Industrial Software Engineering

Publication Type:

Conference/Workshop Paper

Venue:

The 17th Annual IEEE International Conference on the Engineering of Computer Based Systems (ECBS), 2010.

Publisher:

IEEE

DOI:

10.1109/ECBS.2010.21

Abstract

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.

Bibtex

@inproceedings{Latif2039,
author = {Khalid Latif and Tiberiu Seceleanu and Hannu Tenhunen},
title = {Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers. },
editor = {IEEE},
pages = {131--138},
month = {March},
year = {2010},
booktitle = {The 17th Annual IEEE International Conference on the Engineering of Computer Based Systems (ECBS), 2010. },
publisher = {IEEE},
url = {http://www.es.mdu.se/publications/2039-}
}