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Data Cache Locking for Higher Program Predictability

Fulltext:


Authors:

Xavier Vera, Björn Lisper

Publication Type:

Report - MRTC

ISRN:

MDH-MRTC-79/2002-1-SE

Abstract

Caches have become increasingly important with the widening gap between main memories and processors speed. However, they are a source of unpredictability due to their characteristics, resulting in programs behaving in a different way than expected.Cache locking mechanisms adapt caches to the needs of real-time systems. Locking the cache is a solution that trades performance for predictability: at a cost of generally lower performance, the time of accessing the memory is predictable.This paper combines static cache analysis with data cache locking to estimate the worst-case memory performance (WCMP) in a safe, tight and fast way. In order to get predictable cache behavior, we first lock the cache for those parts of the code where the static analysis fails. To minimize the performance degradation, our method loads it, if necessary, with data likely to be accessed. Results show that this scheme is fully predictable, without compromising the performance of the transformed program. When compared to an algorithm that assumes compulsory misses when the state of the cache is unknown, our approach eliminates all overestimation for the set of benchmarks, giving an exact WCMP of the transformed program without any significant decrease in performance.

Bibtex

@techreport{Vera372,
author = {Xavier Vera and Bj{\"o}rn Lisper},
title = {Data Cache Locking for Higher Program Predictability},
number = {ISSN 1404-3041 ISRN MDH-MRTC-79/2002-1-SE},
month = {October},
year = {2002},
url = {http://www.es.mdu.se/publications/372-}
}