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Automatic Load Synthesis for Performance Verification in Early Design Phases - Technical Report


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This paper describes a method to extract hardware characteristics and synthesize a model of a system running in a production environment. It is common to perform characteristics testing at the end of the development process, resulting in complex and costly bug fixes. Using our characteristics model makes it possible to implement continuous performance testing throughout the whole development process. Early characteristics testing is important because it improves system- development efficiency by shortening the total development time. The reduced lead time is an advantage in a competitive market, such as for the telecommunication system we have investigated in this paper. The modeling method is generic and supports any hardware metric. We have modeled the L1-instruction, L1-data and L2-data cache in our experiment. We have applied our method to a large-scale telecommunication system and verified that it is possible to detect performance- related problems during the design phase rather than at the end of the product development cycle.


author = {Marcus J{\"a}gemar and Sigrid Eldh and Andreas Ermedahl and Gabor Andai and Bj{\"o}rn Lisper},
title = {Automatic Load Synthesis for Performance Verification in Early Design Phases - Technical Report},
month = {June},
year = {2016},
url = {}