Jagadish Suryadevara received B.Sc and M.Sc (Applied Mathematics) from Andhra University(Andhra Pradesh, India), and M.Tech (Computer Science) from Jawaharlal Nehru Technological University(AP,India). Previously he worked as Lecturer in Computer Science and Information Systems group, Birla Institute of Technology and Science (BITS),India.
Jagadish Suryadevara has previously worked in the research area of UML specification of concurrent, reactive systems at Tata Institute of Fundamental Research (TIFR), India. His general research interests include UML, formal specification and verification, software architectures, and real-time systems.
Analyzing a wind turbine system: From simulation to formal verification (Oct 2016) Cristina Seceleanu, Morgan Johansson , Jagadish Suryadevara, Gaetana Sapienza, Tiberiu Seceleanu, Stein-Erik Ellevseth , Paul Pettersson Science of Computer Programming, Elsevier (SCICO)
Wind Turbine System : An Industrial Case Study in Formal Modeling and Verification (Oct 2013) Jagadish Suryadevara, Gaetana Sapienza, Cristina Seceleanu, Tiberiu Seceleanu, Stein-Erik Ellevseth , Paul Pettersson Second International Workshop on Formal Techniques for Safety-Critical Systems (FTSCS 2013)
Verifying MARTE/CCSL Mode Behaviors using UPPAAL (Sep 2013) Jagadish Suryadevara, Cristina Seceleanu, Frederic Mallet , Paul Pettersson 11th International Conference on Software Engineering and Formal Methods
Validating EAST-ADL Timing Constraints using UPPAAL (Sep 2013) Jagadish Suryadevara 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA)
Analysis Support for TADL2 Timing Constraints on EAST-ADL Models (Jul 2013) Arda Goknil , Jagadish Suryadevara, Marie-Agnes Peraldi-Frati , Frederic Mallet 7th European Conference on Software Architecture (ECSA)
Timed Automata Modeling of CCSL Constraints (Nov 2012) Jagadish Suryadevara, Ling Yin First International Workshop on Formal Techniques for Safety-Critical Systems
|Master Thesis - UML Profile for ProCOM component model||available|