I did my Masters in Networks and Distributed Systems from Chalmers University of Technology, Sweden.
I joined Mälardalens in Sep 2009 as Ph.D. student.
In Masters thesis, I worked on Multicore environment. I implemented A* algorithm on Nvidias Graphics Card.
In Ph.D. studies I work on hierarchical scheduling for real-time embedded systems. Main focus is on Predictable execution of real-time systems for unicore and multicore platforms.
I am the author/developer of the Multi-Resource server that provides composable hierarchical scheduling on multi-core platforms. We extend traditional server-resources by associating a memory-bandwidth to each server; thus a multi-resource server has both CPU-bandwidth and memory bandwidth allocated to it. The multi-resource servers are useful to provide partitioning, composability and predictability in both hard and soft real-time systems.
I have also developed a Hierarchical Scheduling Framework for FreeRTOS operating system.
A Survey on Testing for Cyber Physical System (Nov 2015) Sara Abbaspour Asadollah, Rafia Inam, Hans Hansson The 27th International Conference on Testing Software and Systems (ICTSS 2015)
Compositional Analysis for the Multi-Resource Server (Sep 2015) Rafia Inam, Moris Behnam, Thomas Nolte, Mikael Sjödin 20th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'15)
Towards improved dynamic reallocation of real-time workloads for thermal management on many-cores (Dec 2014) Rafia Inam, Matthias Becker, Moris Behnam, Thomas Nolte, Mikael Sjödin IEEE Real-Time Systems Symposium Work-in-Progress (WiP) session (RTSS'14)
Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures (Nov 2014) Rafia Inam, Moris Behnam, Mikael Sjödin Seventh Swedish Workshop on Multicore Computing (MCC'14)
|PPMsched - Performance Preserving Multicore Scheduling||finished|
|Multi-resource Server Implementation for Multi-core Architecture||available|
|Adapting Mode Switches into the Hierarchical scheduling||finished|
|Cache-Partitioning for COTS Multi-core Architecture||finished|