Marcus Jägemar is currently working as a capacity and performance expert at Ericsson. He studied Computer Engineering at the Mid Sweden University, Sundsvall, Sweden, and at the University of Greenwich, London, UK. He received his M.Sc. in Computer Engineering from Mid Sweden Univerity in 2000. He has since then mainly been working in various roles within Ericsson, both as a consultant and later as a regular employee. Marcus received his Lic. degree in 2016 and his Ph.D. in 2018. within the DPAC project. His primary academic interest is to improve the performance of large-scale telecommunication systems through efficient shared hardware resource management.
Testing Performance-Isolation in Multi-Core Systems (Jul 2019) Jakob Danielsson, Moris Behnam, Marcus Jägemar, Tiberiu Seceleanu, Mikael Sjödin COMPSAC 2019: Data Driven Intelligence for a Smarter World (COMPSAC 2019)
Enforcing Quality of Service Through Hardware Resource Aware Process Scheduling (Sep 2018) Marcus Jägemar, Sigrid Eldh, Björn Lisper, Moris Behnam, Andreas Ermedahl International Conference on Emerging Technologies and Factory Automation (ETFA'18)
Mallocpool: Improving Memory Performance Through Contiguously TLB Mapped Memory (Sep 2018) Marcus Jägemar International Conference on Emerging Technologies and Factory Automation (ETFA'18)
Measurement-based evaluation of data-parallelism for OpenCV feature-detection algorithms (Jul 2018) Jakob Danielsson, Marcus Jägemar, Tiberiu Seceleanu, Mikael Sjödin, Moris Behnam Staying Smarter in a Smartening World (COMPSAC'18)
A Scheduling Architecture for Enforcing Quality of Service in Multi-Process Systems (Sep 2017) Marcus Jägemar, Moris Behnam, Sigrid Eldh, Andreas Ermedahl International Conference on Emerging Technologies And Factory Automation (ETFA'17)
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