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Cache Memories in Real-Time Systems

Fulltext:


Authors:

Filip Sebek

Note:

<PRE> @TechReport{sebek01cmrts, author = {Filip Sebek}, title = {Cache Memories in Real-Time Systems}, institution = {M"alardalen Real-Time Research Centre}, year = {2001}, key = {cache memories, real time, cache related preemption delay}, number = {01/37}, address = {Department of Computer Engineering, M"alardalen University, Sweden}, month = oct # " 2", url = "http://www.mrtc.mdh.se/php/staff_show.php3?id=0052" } </PRE>

Publication Type:

Report - MRTC

Publisher:

MRTC

ISRN:

MDH-MRTC-37/2001-1-SE

Abstract

The first methods to bound execution time in computer systems with cache memories were presented in the late eighties — twenty years after the first cache memories designed. Today, fifteen years later, methods have been developed to bound execution time with cache memories ... that were state-of-the-art twenty years ago. This report presents cache memories and real-time from the very basics to the state-of-the-art of cache memory design, methods to use cache memories in real-time systems and the limitations of current technology. Methods to handle intrinsic and extrinsic behavior on instruction and data caches will be presented and discussed, but also close issues like pipelining, DMA and other unpredictable hardware components will be briefly presented. No method is today able to automatically calculate a safe and tight Worst-Case Execution Time (WCETC ) for any arbitrary program that runs on a modern high-performance system — there are always cases where the method will cross into problems. Many of the methods can although give very tight WCETC or reduce the related problems under specified circumstances.

Bibtex

@techreport{Sebek290,
author = {Filip Sebek},
title = {Cache Memories in Real-Time Systems},
note = {\textlessPRE\textgreater @TechReport\textbraceleftsebek01cmrts, author = \textbraceleftFilip Sebek\textbraceright, title = \textbraceleftCache Memories in Real-Time Systems\textbraceright, institution = \textbraceleftM{"}alardalen Real-Time Research Centre\textbraceright, year = \textbraceleft2001\textbraceright, key = \textbraceleftcache memories, real time, cache related preemption delay\textbraceright, number = \textbraceleft01/37\textbraceright, address = \textbraceleftDepartment of Computer Engineering, M{"}alardalen University, Sweden\textbraceright, month = oct {\#} {"} 2{"}, url = {"}http://www.mrtc.mdh.se/php/staff{\_}show.php3?id=0052{"} \textbraceright \textless/PRE\textgreater},
number = {ISSN 1404-3041 ISRN MDH-MRTC-37/2001-1-SE},
month = {October},
year = {2001},
publisher = {MRTC},
url = {http://www.es.mdu.se/publications/290-}
}