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Design Challenges in Hardware Development of Time-Sensitive Networking: A Research Plan

Fulltext:


Publication Type:

Conference/Workshop Paper

Venue:

Proceedings of the Cyber-Physical Systems PhD Workshop 2019, "Designing Cyber-Physical Systems "


Abstract

Time-Sensitive Networking (TSN) is a set of ongoing projects within the IEEE standardization to guarantee timeliness and low-latency communication based on switched Ethernet for industrial applications. The huge demand is mainly coming from industries where intensive data transmission is required, such as in the modern vehicles where cameras, lidars and high-bandwidth modern sensors are connected. The TSN standards are evolving over time, hence the hardware needs to change depending upon the modifications. In addition, high performance hardware is required to obtain a full benefit from the standards. In this paper, we present a research plan for developing novel techniques to support a parameterized and modular hardware IP core of the multi-stage TSN switch fabric in VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), which can be deployed in any FieldProgrammable-Gate-Array (FPGA) devices. We present the challenges on the way towards the mentioned goal.

Bibtex

@inproceedings{Ghaderi5606,
author = {Adnan Ghaderi and Masoud Daneshtalab and Mohammad Ashjaei and Mohammad Loni and Saad Mubeen and Mikael Sj{\"o}din},
title = {Design Challenges in Hardware Development of Time-Sensitive Networking: A Research Plan},
booktitle = {Proceedings of the Cyber-Physical Systems PhD Workshop 2019, {"}Designing Cyber-Physical Systems {"} },
url = {http://www.es.mdh.se/publications/5606-}
}