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An Optimizing Model for Memory Fault Tolerance in Onboard Computer

Authors:

Suresh Mathew , Sasikumar Punnekkat, Abdul Salam

Note:

Journal Home page http://www.drdo.com/pub/dsj/dsjhome.htm

Publication Type:

Journal article

Venue:

Defense Science Journal

Publisher:

DRDO published by DESIDOC

Abstract

This paper presents an optimising model for integrating the traditional reliability prediction methodology with simple analytical techniques to facilitate the designer to decide upon the memory fault-tolerant choices of an onboard computer. In this exercise, the hardware reliability estimates of a circuit without any error correction as well as that of a circuit with error detection and correction were calculated. The failure rates of each component and soldering have been accounted for in these prediction procedures. A suitable probability distribution is chosen for data errors and is analytically combined with the hardware reliability predictions to study the trade-offs. An optimum strategy for introducing the hardware error correction logic in the circuit is presented.

Bibtex

@article{Mathew786,
author = {Suresh Mathew and Sasikumar Punnekkat and Abdul Salam},
title = {An Optimizing Model for Memory Fault Tolerance in Onboard Computer},
note = {Journal Home page http://www.drdo.com/pub/dsj/dsjhome.htm},
volume = {52},
number = {1},
month = {January},
year = {2002},
journal = {Defense Science Journal},
publisher = {DRDO published by DESIDOC},
url = {http://www.es.mdu.se/publications/786-}
}