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An UPPAAL Model for Formal Verification of Master/Slave Clock
Publication Type:
Conference/Workshop Paper
Venue:
6th IEEE Intl Workshop on Factory Communication Systems (WFCS)
Publisher:
IEEE Electronics Society
Abstract
Many distributed applications require a clock synchronization
service. We have previously proposed a clock
synchronization service for the Controller Area Network
(CAN), which we have claimed to provide highly synchronized
clocks even in the occurrence of faults in the system.
In this paper we substantiate this claim by providing a formal
model and verification of our fault tolerant clock synchronization
mechanism. We base our modeling and verification
on timed automata theory as implemented by the
model checking tool UPPAAL. In the modeling we introduce
a novel technique for modeling drifting clocks. The
verification shows that a precision in the order of 2 μs
is guaranteed despite node’s faults as well as consistent
channel faults. It also shows that inconsistent channel
faults may significantly worsen the achievable precision,
but that this effect can be reduced by choosing a suitable
resynchronization period.
Bibtex
@inproceedings{Rodriguez-Navas920,
author = {Guillermo Rodriguez-Navas and Juli{\'a}n Proenza and Hans Hansson},
title = {An UPPAAL Model for Formal Verification of Master/Slave Clock},
month = {June},
year = {2006},
booktitle = {6th IEEE Intl Workshop on Factory Communication Systems (WFCS)},
publisher = {IEEE Electronics Society},
url = {http://www.es.mdu.se/publications/920-}
}