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Experiences with VHDL and FPGAs

Authors:

Lennart Lindh, Johan Stärner

Publication Type:

Journal article

Venue:

Journal of Systems Architecture

Publisher:

Euromicro

Abstract

In order to remain competitive, a company needs to reduce its product development time, and consequently the development time for prototyping has to be reduced as well. One way to decrease the development time of a product is to synthesize the design description automatically to FPGAs (Field Programmable Gate Arrays). This article describes the experience of implementing a real-time kernel in hardware using VHDL for behavioral and data flow (RTL) description, simulation, synthesis to gate level, back-annotation and programming FPGAs for a prototype.

Bibtex

@article{Lindh96,
author = {Lennart Lindh and Johan St{\"a}rner},
title = {Experiences with VHDL and FPGAs},
volume = {42},
pages = {97--104},
month = {January},
year = {1996},
journal = {Journal of Systems Architecture},
publisher = {Euromicro},
url = {http://www.es.mdu.se/publications/96-}
}