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Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with real-time requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified together, resulting in a rapidly increasing verification complexity. Predictable and composable systems have been proposed to address this problem. Predictable systems provide bounds on performance, enabling formal analysis to be used as an alternative to simulation. Composable systems isolate applications temporally, enabling them to be verified independently.
Predictable and composable systems are built from predictable and composable resources. This presentation discusses concepts, architecture, configuration, and modeling of a predictable and composable memory controller. The controller design is general and supports both SRAM and SDRAM and a wide range of arbiters, making it suitable for many predictable and composable systems. The memory controller is supported by a configuration tool that automatically computes appropriate configuration settings, given bandwidth and latency requirements of the memory clients. The modeling approach is based on a shared-resource abstraction that covers any combination of supported memory and arbiter and enables system-level performance analysis with a variety of well-known frameworks, such as network calculus or data-flow analysis.
The memory controller is positioned with respect to existing work, targeting either firm real-time (FRT) systems or soft/no real-time (SRT/NRT) systems. The requirements of complex mixed real-time (MRT) systems, which contain a combination of FRT, SRT, and NRT memory clients, are presented and we explain why current controllers are unable to satisfy these requirements. As a direction for future research, we discuss how current FRT and SRT/NRT memory controllers may evolve into MRT controllers, suitable for complex systems-on-chips.
Benny Åkesson was born in Landskrona, Sweden in 1977. He earned a M.Sc. degree in Computer Science and Engineering at Lund Institute of Technology, Sweden in 2005. In 2010, Dr. Åkesson received his Ph.D. degree in Electrical Engineering at Eindhoven University of Technology, the Netherlands, on the topic of "Predictable and Composable SoC Memory Controllers". This research was conducted in collaboration with NXP Semiconductors. Dr. Åkesson is currently working as an assistant professor at the Eindhoven University of Technology, where he is leading the memory research team in the Electronic Systems group at the faculty of Electrical Engineering. His research interests include memory controller architectures, real-time resource scheduling, performance modeling, and virtualization. He is the author of a book about memory controllers for real-time embedded systems.