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CAMP: A Hierarchical Cache Architecture for Multi-core Mixed Criticality Processors

Authors:

Arun Sukumaran Nair , Geeta Patil , Biju Raveendran , Sasikumar Punnekkat

Research group:

Dependable Software Engineering

Publication Type:

Journal article

Venue:

International Journal of Parallel, Emergent and Distributed Systems

Publisher:

Taylor and Francis Group, UK

DOI:

https://doi.org/10.1080/17445760.2023.2293913

Abstract

CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems.

Bibtex

@article{Sukumaran Nair 6849,
author = {Arun Sukumaran Nair and Geeta Patil and Biju Raveendran and Sasikumar Punnekkat},
title = {CAMP: A Hierarchical Cache Architecture for Multi-core Mixed Criticality Processors},
month = {December},
year = {2023},
journal = {International Journal of Parallel, Emergent and Distributed Systems},
publisher = {Taylor and Francis Group, UK},
url = {http://www.es.mdu.se/publications/6849-}
}