Matthias Becker is a postdoc researcher at KTH Royal Institute of Technology since February 2018. He received his B.Eng. degree in Mechatronics/Automation Systems from the University of Applied Sciences Esslingen, Germany in 2011. In the year 2013 he got his M.Sc. degree in Computer Science specializing in embedded computing from the University of Applied Sciences Munich, Germany. He received his Licentiate and PhD degree in Computer Science and Engineering from Mälardalen University in 2015 and 2017 respectively.
Matthias has been a visiting researcher at CISTER - Research Centre in Real-Time and Embedded
Computing Systems in Porto, Portugal for two months in 2015 and for three months in 2016.
Matthias' research is in the field of many-core real-time systems with particular interest in predictable execution frameworks for industrial systems. He is involved in the research project PREMISE (Predictable Multicore Systems).
Execution Frameworks for Many Core Platforms:
Seminar talk on Contention Free Execution of Automotive Applications on a Clustered Many-Core Platform at the CISTER Research Centre in Realtime and Embedded Computing Systems, Porto Portugal. The talk is based on the paper Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform (ECRTS, July 2016) .
MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies
MECHAniSer is a tool to compute end-to-end delays in cause-effect chains. In such chains, each task is independently triggered, possibly at different rates. The communication between task is based on register communication. The current version of the tool is available at www.mechaniser.com.
The current version of the tool computes the minimum and maximum data age of the cause-effect chains in the system. This is done without prior knowledge of the concrete schedule, hence the analysis can already be applied in early design phases. In addition, the tool generates job-level dependencies to restrict the data propagation between tasks such that the possible end-to-end latency does not exceed the specified age constraint. The tool was presented in the paper MECHAniSer - A Timing Analysis and Synthesis Tool for Multi Rate Effect Chains with Job-Level Dependencies (WATERS, July 2016), and the theoretical part of the tool was published in the paper Synthesizing Job-Level Dependencies for Automotive Multi-Rate Effect Chains (RTCSA, August 2016).
Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling (Jan 2021) Lamija Hasanagic, Tin Vidovic, Saad Mubeen, Mohammad Ashjaei, Matthias Becker 26th Asia and South Pacific Design Automation Conference (ASP-DAC'21)
From AMALTHEA to RCM and Back: a Practical Architectural Mapping Scheme (Aug 2020) Alessio Bucaioni, Matthias Becker, John Lundbäck , Harald Mackamul 46th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2020)
Modelling and Timing Analysis of Real-time Applications on Evolving Automotive E/E Architectures using Rubus-ICE (Dec 2019) Alessio Bucaioni, John Lundbäck , Mattias Gålnander , Kurt-Lennart Lundbäck , Mohammad Ashjaei, Matthias Becker, Saad Mubeen Open Demo Session of Real-Time Systems 2019 (RTSS@Work'19)
Static Allocation of Parallel Tasks to Improve Schedulability in CPU-GPU Heterogeneous Real-Time Systems (Oct 2019) Nandinbaatar Tsog, Matthias Becker, Fredrik Bruhn, Moris Behnam, Mikael Sjödin IEEE 45th Annual Conference of the Industrial Electronics Society (IECON'19)
Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems (Oct 2018) Matthias Becker, Saad Mubeen 44th Annual Conference of the IEEE Industrial Electronics Society (IECON'18)
|DPAC - Dependable Platforms for Autonomous systems and Control||active|
|Network-on-Chip routing in real-time many-core systems||in progress|
|Communication mechanisms among instances of a many-core real-time system||finished|
|End-to-End Timing Analysis of Task-Chains||finished|
|Offline Scheduling of Task Sets with Complex End-to-End Delay Constraints||finished|